X3

- Design in accordance with the JEDEC standard;
- New architecture of DDR4 and new technical solution to reduce power consumption by 30% and improve speed by 1.7 times;
- Architecture of Point to Point Topology to improve efficiency of data transmission;
- Bank Group to greatly increase the memory speed;
- Write CRC to greatly increase the read/write reliability of data;
- PPR separated programming operation to support on-line correction of address lines;
- FGR refresh and adjustment to reduce refresh latency and improve effective bandwidth;
- Four channels supported to increase performance by 40%;
- Rigorous solution to select high-quality chips only.