REG Memory VLP


- Design in accordance with the JEDEC standard;
- 18.75mm-high VLP;
- Built-in ECC and Parity functions;
- Synchronous data signal and consistent driving force in high-speed multi-load environment;
- High-standard PCB design with 8-10 layers of boards;
- 30 μ industrial gold-finger process;
- Server-class original DRAM chips selected.


Specification parameters


Model BandwidthCapacityVoltageWorking temperatureCL Pin    Gold   finger
Low temperatureHigh temperature
-40°C-20°C0°C85°C95°C
DDR4-2666   REG UDIMM VLPPC4-213004GB-8GB1.2V
****CL19288-pin30μ"
DDR4-2133   REG UDIMM VLPPC4-170004GB-8GB1.2V*****CL15288-pin30μ"
   *Indicates optional